1. Field of the Invention
Embodiments of the present invention relate generally to a semiconductor memory device. More particularly, embodiments of the invention relate to a method and apparatus for programming a flash memory device having multi-level cells.
A claim of priority is made to Korean Patent Application No. 2005-69566, filed Jul. 29, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
A flash memory device is a nonvolatile memory device capable of being electrically programmed and erased. Flash memory devices have become increasingly popular in recent years as the demand for high capacity and high-speed nonvolatile memories has continued to increase in application areas such as portable electronic devices and code memories.
Flash memory can be broadly classified into NAND type flash memory and NOR type flash memory. NOR type flash memory has a structure wherein a plurality of memory cells are connected in parallel to a bit line, and NAND type flash memory has a structure wherein a plurality of memory cells are connected in series to a bit line. Because the memory cells in NOR type flash memory are connected to bit lines in parallel, NOR type flash memory allows random access to stored data. In contrast, NAND type flash memory only allows sequential access to data. As a result of their different cell arrangements, NOR type flash memory tends to provide faster read times than NAND type flash memory, and therefore NOR type flash memory is often used in applications requiring high read speed such as the storage of program code. On the other hand, NAND type flash memory tends to have higher integration density and higher program and erase speeds than NOR type flash memory, and therefore it is often used for applications such as long term data storage.
In an effort to improve the integration density of both NOR and NAND type flash memory devices, researchers have developed flash memory devices having memory cells capable of storing more than one bit of information. These memory cells are commonly referred to as “multi level cells” (MLC) and devices containing MLCs are referred to as MLC devices. The operation of a conventional MLC flash memory device is described below with reference to FIGS. 1 and 2.
FIG. 1 is a drawing illustrating a threshold voltage distribution for a MLC capable of storing two bits of information, i.e., a most significant bit (MSB) and a least significant bit (LSB). Referring to FIG. 1, the MLC can store the data values ‘11’, ‘10’, ‘00’, and ‘01’, by adjusting the threshold voltage of the cell in ascending order. For example, where the MLC has a first threshold voltage, the MLC stores the data value ‘11.’ Where the MLC has a second, higher threshold voltage, the MLC stores the data value ‘10,’ and so on. In general, the data value ‘11’ corresponds to an erased state of the MLC, and programming of the MLC begins from the erased state.
FIG. 2A is a state transition diagram illustrating a sequence for programming data into the MLC. In FIGS. 2A and 2B, states are labeled ‘11’, ‘10’, ‘00’, and ‘01’ to correspond to states of the MLC when it stores these respective data values. These states can also be referred to as state ‘11’, state ‘10’ and so on. According to the state transition diagram shown in FIG. 2A, the MLC is programmed by first programming its LSB, and then programming its MSB.
A transition of the MLC from state ‘11’ to state ‘10’ by changing its LSB is executed through a path denoted {circle around (1)} in FIG. 2A. A transition of the MLC from state ‘11’ to state ‘01’ by changing its MSB is performed along a path denoted {circle around (3)} in FIG. 2A. A transition of the MLC from state ‘11’ to state ‘00’ by changing both its LSB and its MSB is executed along paths denoted. {circle around (1)} and {circle around (2)} in FIG. 2A. Paths {circle around (2)}, and {circle around (3)} correspond to program procedures which are performed to program the MSB after programming the LSB. Where the LSB is programmed first and the MSB is programmed second, it is assured from the state transition diagram of FIG. 2 that the program is performed favorably.
FIG. 2B is a state transition diagram illustrating why the LSB cannot be programmed after the MSB is programmed, where the threshold voltages corresponding to the logic states of the MLC are arranged as shown in FIG. 1. First, consider a program operation wherein the MLC is programmed from state ‘11’ to state ‘00’. The program operation should first change the MLC from state ‘11’ to state ‘01’ through a path {circle around (4)} where the MSB is converted from ‘1’ into ‘0’. Next, the program operation should change the MLC from state ‘01’ to state ‘00’ through a path {circle around (5)} where the LSB is converted from ‘1’ to 0’. Unfortunately, however, a MLC with the threshold voltage distributions and corresponding states shown in FIG. 1 cannot be changed from state ‘01’ to ‘00’ without first erasing the MLC. In other words, conventional techniques do not allow the threshold voltage of the MLC to be reliably decreased directly from the threshold voltage distribution labeled ‘01’ to the threshold voltage distribution labeled ‘00’. Accordingly, where the threshold voltages are assigned to states ‘11’, ‘10’, ‘00’, and ‘01’ as shown in FIG. 1, the programming sequence where the LSB is programmed first and the MSB is programmed next must be used and not the programming sequence where the MSB is programmed first and the LSB is programmed next.
Unfortunately, the above ordering constraint on the programming sequence can have a negative impact on the overall performance of a flash memory system, since there may be cases where it is advantageous to program the MSB first and then program the LSB. For example, the ordering constraint prohibits an application from programming only the MSB and then later programming the LSB. In other words, the constraint prohibits true random access to MLCs.